Microelectronic semiconductor devices such as transistors, resistors and diodes are conventionally fabricated in monocrystalline silicon substrates and in monocrystalline silicon films on sapphire substrates. A plurality of such devices may be interconnected to form a monolithic integrated circuit structure on a "chip," i.e., a relatively small piece of a substrate wafer. Devices are fabricated on sapphire substrates, and termed silicon-on-sapphire or SOS structures, when it is desired to isolate individual devices from one another. Such isolation may be important, for example, when the ambient environment in which the chip is to operate includes ionizing radiation. Compared to structures fabricated in bulk silicon substrates, SOS structures in such environments provide no crosstalk among devices on a chip and no latchup between N channel and P channel field effect transistors (FETs) in the case of complementary metal oxide semiconductor (CMOS) structures.
However, conventional SOS structures also have certain inherent disadvantages. When the silicon film on the sapphire surface is relatively thin, i.e. less than approximately 0.3 microns (3000 Angstroms), the crystallographic quality thereof is significantly reduced. This in turn causes charge carrier mobility to be relatively low and minority carrier lifetime to be relatively short. Additionally, compared to silicon substrates, sapphire substrates are relatively expensive and are in shorter supply.
In commonly assigned U.S. patent application Ser. No. 818,032, METHOD FOR MAKING A SILICON-ON-INSULATOR SUBSTRATE, L. L. Jastrzebski, filed Jan. 13, 1986, now pending a process is described for fabricating a silicon-on-insulator (SOI) substrate having its foundation on a silicon wafer. Although the SOI structure disclosed therein is effective, the fabrication process presents certain inherent limitations in thickness of the oxide insulator layer and uniformity of thickness of the oxide insulator layer. The present invention overcomes these limitations.